This invention relates to a substrate for semiconductor flip chip package, and a process to fabricate the flip chip device with the substrate.
Flip chip technology is one of the most frequently used package technology for chip scale package. As the flip chip technology can employ area array to dispose bump pad and be connected to the carrier through a bump, it can reduce the packaging area and shorten the transmission path of the signal. Traditional type of bump pad design of the substrate can be classified into SMD (Solder Mask Defined) type and NSMD (Non-Solder Mask Defined) type. Each of these two types of bump pad design has its own merits and demerits. As a result, there is no verdict on this matter one way or another.
FIGS. 1 and 2 are cross-sectional views of a flip chip package of the NSMD type as an example in the prior art. As shown in FIGS. 1 and 2, a plurality of bumps 110 is formed on the active surface of the chip 120. The chip 120 is to be attached to a substrate 130, and is electrically connected to the substrate 130 through the bump pads 140 by the bumps 110. In general, the substrate 130 is composed of one or more layers of patterned conducting (e.g., copper) foil and insulating layers stacked in an alternating sequence, together with etching holes (not shown) in the insulating layers for interconnecting the patterned conducting layers. The substrate 130 has its surface coated with a solder mask layer 150, and exposes only the bump pads 140 for connection to the bumps of the chip 120.
As shown in FIG. 2, a reflow process is employed in the conventional method to heat the bump 110. The heated bumps 110 will melt and form good bonding with the bump pads 140. As an example, in the case of Pd-Tin bumps, where the bumps 110 will melt at 183° C., the bump will be heated to above 200° C. to obtain a good wetting function to form good bonding with the bump pad. Subsequently, an underfill material (not shown) is employed to fill the space between the chip 120 and the substrate 130 as shown in FIG. 2. This is to protect the bumps 110 from being “fatigue collapse” due to thermal stress resulted from difference between the coefficient of thermal expansion of the chip 120 and that of the substrate 130.
Such bump to bump pad connection method suffers from several problems when there are defects or alignment problems on the chip 120 or the substrate 130. Typical defects include the position offset of either left-offset or right-offset between bumps 110 and the bump pads 140 as shown in FIG. 3, elevation offset between the coplanarity of the substrate 130 to the chip 120 as shown in FIG. 4, or between the bumps 112 as shown in FIG. 5, position offset due to the misalignment between the distribution of the array of the bumps 110 to the distribution of the bump pads 140 on the substrate 130 as shown in FIG. 6 and FIG. 7. The following describes in details the above defects in the flip chip fabricated by conventional process.
As observed in FIG. 3, if there is misalignment of the bumps 110 and bump pads 140 when the chip 120 is placed on the bump pad, there will be position offset problem wherein part of the bumps 110 are unable to touch the bump pads 140, or the bumps 110 are able to touch the bump pads 140 but the contact areas are too small to have a good contact between the bumps 110 and the bump pads 140. In this case, bad solder joint will be formed between the bumps 110 and the bump pads 140 with low electrical conductance, or there are no electrical contact between the bumps 110 and the bump pads 140 at all. In either case, the bumps 110 are said to have been cracked due to the thermal stress in the reflow process.
Similarly, if there are coplanar problem between the chip 120 and the substrate 130, there will be elevation offset between the bumps 110 and the bump pads 140 as shown in FIG. 4. In this case, due to an imperfection 132 in the substrate 140, one or more of the bumps 110 are unable to touch the bump pads 140, or the bumps 110 are able to touch the bump pads 140 but the contact areas are too small to have a good contact between the bumps 110 and the bump pads 140. In this case, bad solder joint will be formed between the bumps 110 and the bump pads 140 with low electrical conductance, or there are no electrical contact between the bumps 110 and the bump pads 140 at all. In either case, the bumps 110 are said to have been cracked due to the thermal stress in the reflow process.
Elevation offset problem can also be caused by non-uniformity in the sizes of the bumps 110. As shown in FIG. 5, one or more of the bumps 112 are too small such that they are unable to touch the bump pads 140, or the bumps 112 are able to touch the bump pads 140 but the contact areas are too small to have a good contact between the bumps 112 and the bump pads 140. In this case, bad solder joint will be formed between the bumps 112 and the bump pads 140 with low electrical conductance, or there are no electrical contact between the bumps 112 and the bump pads 140 at all. In either case, the bumps 112 are said to have been cracked due to the thermal stress in the reflow process.
The position offset can also be caused by the misalignment between the distribution of the array of the bumps 110 to the distribution of the bump pads 140 on the substrate 130 as shown in FIG. 6 (showing a misaligned bump 113 straddling a bump pad 142 and a solder mask portion 152), and FIG. 7 (showing a bump 114 straddling a misaligned bump pad 142 and solder mask portion 152). In these cases, only part of the bumps 110 can be aligned to the bump pads 140, other bumps 110 are unable to touch the bump pads 140, or the bumps 110 are able to touch the bump pads 140 but the contact areas are too small to have a good contact between the bumps 110 and the bump pads 140. In this case, bad solder joint will be formed between the bumps 110 and the bump pads 140 with low electrical conductance, or there are no electrical contact between the bumps 110 and the bump pads 140 at all. In either case, the bumps 110 are said to have been cracked due to the thermal stress in the reflow process
FIGS. 14, 15 and 16 are simplified cross sectional side view of prior art flip chips (U.S. Pat. No. 6,975,035) illustrating a chip attached to a substrate, wherein the bumps are substantially inserted into the recesses of the substrate with different mounting method. The bumps 110 in FIG. 14 are directly bonded to the metallic pads of the substrate, whereas the bumps 110 in FIG. 15 were coated with conductive paste 170 before being inserted into the recesses and interconnections are formed between the conductive paste and the pads. In FIG. 16, the conductive paste 170 is deposited onto the pads instead of the bumps, and interconnections are formed between the bumps 110 and the conductive paste 170. The package structure as shown in FIG. 14 does not solve the potential elevation offset problem as depicted in FIG. 4. Mounting method illustrated in FIGS. 15 and 16 solves the noncoplanarity problem introduced by inconsistent bump height and imperfection of the substrate, but the potential risk of positional offset as observed in FIG. 3 is still exist. For FIG. 15, the conductive paste 170 cannot spread over the exposed area of the pads. And for FIG. 16, only part of the bump surface is contacting the conductive paste 170. The conducting areas in both cases are small and thus the solder joint reliability is low. Also, splitting of conductive paste 170 onto the surface of the substrate 130 would occur when the bumps 110 are inserted into the recesses in FIG. 16.